The integration degree of a semiconductor device gradually increases to realize a higher capacity, higher speed and lower power consumption. Thus, various problems may occur that deteriorate transistor characteristics. For example, a short channel effect such as a punch-through, a drain induced barrier lowering, or a sub-threshold swing, may occur when the length of a channel is shortened. In addition, current leakage and parasite capacitance between a junction region and a substrate may increase.
To overcome one or more of the above problems, a three dimensional device has been researched. For example, a dual gate transistor or a fin field effect transistor has been developed.
The fin field effect transistor may be formed using a silicon fin protruding from a substrate. A gate electrode may be formed on the silicon fin. The silicon fin and the gate electrode may extend in a first direction and a second direction, respectively. The second direction may be substantially perpendicular to the first direction. The silicon fin may be located under the gate electrode corresponding to channel region. The gate electrode may cover both sidewalls of the silicon fin. The channel region may be effectively controlled because the channel region is controlled by the gate electrode covering both sidewalls of the silicon fin. In addition, source/drain regions may be formed at portions of the silicon fin adjacent to the channel region. Thus, a punch-through may be reduced between the source/drain regions.
However, the gate induced drain leakage (GIDL) and junction leakage of such a fin field effect transistor may be larger than those of a conventional planar-typed transistor. Thus, when a dynamic random access memory (DRAM) includes a fin field effect transistor, the retention time (i.e., a refresh time) may be reduced due to increases in the GIDL and the junction leakage.